# Layout Engineering Manager at OLIX

> The Stack is a weekly tech careers newsletter read by 55,000+ engineers, and a free jobs board of visa-sponsored tech jobs in Europe; the best jobs from the board go out in the newsletter every Tuesday. This is one job from the board.

> Responsibilities: - Architect and execute full‑custom analog

- **Company:** OLIX (https://jobs.trythestack.co/companies/olix)
- **Location:** Bristol , United Kingdom
- **Work arrangement:** On-site
- **Employment type:** Full-time
- **Experience level:** 10+ years
- **Visa sponsorship:** Offered, according to the listing
- **Key skills:** Analog Layout, Mixed-Signal IC Layout, CMOS FinFET, Cadence Virtuoso, Physical Verification, SKILL Scripting, Parasitic Extraction, EM/IR-drop Sign-off, Floor-planning, PDK/IP Library Management, Tape-out Execution, People Management
- **Posted by employer:** 2026-05-05
- **Added to The Stack:** 2026-05-05
- **Status:** May no longer be active (posted more than 60 days ago)
- **Apply:** https://jobs.ashbyhq.com/olix/342f6c9b-5e92-40af-aeba-35d1e7bebeb2 (the employer's own application page)
- **Human page:** https://jobs.trythestack.co/jobs/layout-engineering-manager-olix

## About the role

Responsibilities:
- Architect and execute full‑custom analog and mixed‑signal layouts (high-speed ADC/DAC, SerDes front-ends, PLLs/CDRs, TIAs, LDOs, bandgaps) in advanced FinFET nodes.
- Own floor-planning, power-grid strategy, shielding, and signal-integrity for high-speed blocks; collaborate with circuit designers to meet PPA and noise/matching targets.
- Lead block- and chip-level AMS integration (hierarchical assembly, abutment, ESD/latch-up, antenna mitigation, seal-/PAD-ring design) and manage tape-out activities.
- Drive physical verification and post-layout sign-off: DRC/LVS, parasitic extraction, EM/IR analysis across PVT corners; iterate to closure.
- Build layout automation (SKILL scripts, parameterized PCells), manage PDK/IP libraries and design-data workflows, and coordinate cross-functional execution with internal and external partners.

Requirements:
- 8+ years of full‑custom analog/mixed‑signal layout experience with at least three taped-out products containing high-speed analog content.
- Tape-out experience in advanced CMOS FinFET (≤16 nm) with deep understanding of FinFET-specific rules, matching, and parasitics.
- Expert command of Cadence Virtuoso (Layout/Suite, Schematic, ADE) and experience with physical‑verification flows (Calibre or Pegasus/PVS).
- Hands-on experience with parasitic extraction and EM/IR tools (xACT/PEX, Quantus QRC, Voltus, Totem or equivalent) and post-layout closure methodology.
- Proficiency in SKILL scripting, layout automation, GDSII/OASIS flows, PDK/IP management, strong leadership and cross-team coordination skills.

## Responsibilities

Lead the architecture, planning, and execution of full-custom analog and mixed-signal layouts for high-speed data converters and SerDes in advanced FinFET nodes. Manage the layout PDK/IP library, drive physical verification sign-off, and lead teams of internal and external design partners.

## Requirements

Requires 8+ years of experience in full-custom analog/mixed-signal IC layout with at least three taped-out products in advanced CMOS FinFET (16nm or below). Must be an expert in Cadence Virtuoso and physical verification tools, with proficiency in SKILL scripting and leadership experience.

## FAQ

- **Is this Layout Engineering Manager role still open?** It was posted on 2026-05-05. Listings more than 30 days old may no longer be active, so check OLIX's site before applying.
- **Does OLIX offer visa sponsorship?** This listing is marked as offering visa sponsorship. Eligibility rules are set by the employer, so check the details on OLIX's site.
- **Where is this role located?** The listing gives the location as Bristol , United Kingdom. It is marked on-site.
- **What skills does this role ask for?** The listing names: Analog Layout, Mixed-Signal IC Layout, CMOS FinFET, Cadence Virtuoso, Physical Verification, SKILL Scripting, Parasitic Extraction, EM/IR-drop Sign-off, Floor-planning, PDK/IP Library Management, Tape-out Execution, People Management.

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## Notes for agents

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