Layout Engineering Manager at OLIX

Bristol , United Kingdom

on-site · full_time · 206000 · Visa sponsorship

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Responsibilities:
- Architect and execute full‑custom analog and mixed‑signal layouts (high-speed ADC/DAC, SerDes front-ends, PLLs/CDRs, TIAs, LDOs, bandgaps) in advanced FinFET nodes.
- Own floor-planning, power-grid strategy, shielding, and signal-integrity for high-speed blocks; collaborate with circuit designers to meet PPA and noise/matching targets.
- Lead block- and chip-level AMS integration (hierarchical assembly, abutment, ESD/latch-up, antenna mitigation, seal-/PAD-ring design) and manage tape-out activities.
- Drive physical verification and post-layout sign-off: DRC/LVS, parasitic extraction, EM/IR analysis across PVT corners; iterate to closure.
- Build layout automation (SKILL scripts, parameterized PCells), manage PDK/IP libraries and design-data workflows, and coordinate cross-functional execution with internal and external partners.

Requirements:
- 8+ years of full‑custom analog/mixed‑signal layout experience with at least three taped-out products containing high-speed analog content.
- Tape-out experience in advanced CMOS FinFET (≤16 nm) with deep understanding of FinFET-specific rules, matching, and parasitics.
- Expert command of Cadence Virtuoso (Layout/Suite, Schematic, ADE) and experience with physical‑verification flows (Calibre or Pegasus/PVS).
- Hands-on experience with parasitic extraction and EM/IR tools (xACT/PEX, Quantus QRC, Voltus, Totem or equivalent) and post-layout closure methodology.
- Proficiency in SKILL scripting, layout automation, GDSII/OASIS flows, PDK/IP management, strong leadership and cross-team coordination skills.